Deperlify now on VLSI Tools

Deperlify (“De – Perl – ify”), the newest addition to the VLSI Tools family, is now up on the website thanks to some help from Dave Fick. Deperlify allows you to embed Perl blocks into your Verilog code, and a simple post processor executes the inline Perl code replacing it with the resulting output into a final Verilog file. This allows you to use the power of Perl scripting to generate complex Verilog structures while still ensuring a known synthesizable result. Perl based datastructures can be shared between files to allow for greater code reuse than is normally possible in Verilog. Verilog constructs can be parametrized with greater ease and intuition than standard Verilog form. Copy-paste errors can be greatly reduced with Deperlify. ¬†Download a copy at